The Semiconductor memory technology is a key one in the microelectronic technology. With the information technology's focus changing from network and computation to storage, researches on the memory technology are becoming a critical research direction in the information technology. Current researches on the memory technology mainly focus on a high-density, high-performance non-volatile FLASH. As a semiconductor device is scaled down, the conventional FLASH technology encounters much severer technical difficulties such as crosstalk, low write-in speed etc. It is difficult to meet the requirement of the memory technology at 20 nm technology node and beyond. Therefore, it is desirable to develop new memory technology to meet mass storage requirements.
Recently, a variable resistance memory technology attracts many researchers' attention. The variable resistance memory technology is believed to be a key technology at 20 nm technology node and beyond. A resistance random access memory (RRAM) distinguishes two states by a reversible conversion of the storage medium between a high resistance and a low resistance under the effect of an electric signal.
The memory cell has a structure formed by successively stacking three layers of an upper electrode, a variable resistance material and a lower electrode. Such a memory cell is advantageous because it has a simple structure, can be easily manufactured and compatible with the prior CMOS process. 3D integration of variable resistance memory cells may achieve high density storage of data, and may be used in various applications such as solid state disk.
Due to a crosstalk effect between the variable resistance memory cells in a conventional cross-bar configuration, the conventional variable resistance memory technology needs to use a diode or a section transistor to select a memory cell. 1D1R and 1T1R are two typical memory configurations. 3D variable resistance memory is 3D integration in the two typical memory configurations. FIG. 1 is a schematic diagram of a semiconductor memory device in 1D1R configuration in the prior art. As shown in FIG. 1, although the 1D1R type 3D variable resistance memory device may increase a storage density to some extent, it can not bring an apparent change in a height of the memory cell because a diode in the memory cell consists of a PN junction. The conventional PN junction has a height larger than 100 nm. Moreover, a layer of intrinsic silicon is used in the PN junction so as to increase a positive bias current and suppress a negative bias current. Furthermore, a metal barrier layer is used for suppressing interdiffusion of metal in a metal electrode and P-type silicon. These additional layers increase a thickness of the memory cell, and hinder an arrangement of the memory cells in multiple levels. For example, it is difficult to perform etching on a multilayer structure. More importantly, in a case that the memory cells are stacked in multiple levels, ion implantation for forming the PN junction and subsequent activation of impurities should be performed at a relatively high temperature. Performances of previously-formed memory cells may be affected when forming subsequent memory cells, which is disadvantageous for high reliable operation of the memory device. Therefore, the 1T1R type 3D memory technology may have a greater potential in high-density integration than the 1D1R type 3D variable resistance memory. For example, more levels of memory cells may be integrated in the 1T1R type 3D memory technology by adjusting the thicknesses of respective storage layers.
FIG. 2 is a schematic diagram of the 1T1R type semiconductor memory device with a right and a left electrodes in the prior art. FIG. 3 is a schematic diagram of the 1T1R type semiconductor memory device with an upper and a lower electrodes in the prior art. As shown in FIGS. 2 and 3, a storage area is accessed by using a selection transistor, regardless of the variable resistance unit structure with the right and the left electrodes or the variable resistance unit structure with the upper and the lower electrodes, in the 1T1R type 3D memory technology. It requires that the selection transistor has a large on/off ratio, wherein a large on-state current is used for programming and a low off-state current is used for avoiding crosstalk. However, the implementation of the large on/off ratio departs from the requirement of reducing a layout size of the transistor in the high-density integration of the 3D memory device. Therefore, the conventional 3D structure must seek tradeoff between the density and performances, which is not a good solution. Similar to a DRAM with a conventional 1T1C structure, the dimension of a single selection transistor will be a bottleneck for a further reduction in scaling down.
The inventor recognized that the prior approaches in the 3D semiconductor memory device had the drawback that the transistor could not have a large on/off ratio while having a reduced layout size of the transistor.